Generally, an image sensor is a semiconductor device for converting an optical image into an electric signal. There are a number of different types of semiconductor-based imagers, including charge coupled devices (CCDs), photodiode arrays, charge injection devices, hybrid focal plane arrays, etc. The various types of image sensors may be broadly categorized as charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) image sensors.
CCDs are often employed for image acquisition and enjoy a number of advantages which makes it attractive for many small size imaging applications. CCDs are also produced in large formats with small pixel size and they employ low noise charge domain processing techniques.
However, CCD imagers suffer from a number of disadvantages. For example, CCDs are susceptible to radiation damage; CCDs are often expensive to manufacture; CCDs require good light shielding to avoid image smear and; CCDs have a high power dissipation for large arrays. CCD imagers also have a complicated driving method and a complicated fabrication process requiring a multi-phased photo process. A control circuit, a signal processing circuit, an analog to digital (A/D) converter circuit, etc., cannot be easily integrated into a CCD chip, thereby inhibiting the use of CCDs in compact size products. While there have been some attempts to integrate on-chip signal processing with a CCD array, these attempts have not been entirely successful. CCDs also must transfer an image by linear charge transfers from pixel to pixel, requiring that the entire CCD array be read out into a memory before individual pixels or groups of pixels may be accessed and processed. This takes time. CCDs may also suffer from incomplete charge transfer from pixel to pixel during charge transfer which also results in image smear.
Because of the inherent limitations in CCD technology, there has been increased interest in CMOS imagers for possible use as low cost imaging devices. CMOS image sensors first came to the fore in relatively low-performance applications where shuttering was not required, scene dynamic range was low, and moderate to high noise levels could be tolerated. A CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, star trackers, motion detection systems, image stabilization systems and high-definition television imaging devices.
The advantages of CMOS imagers over CCD imagers are that CMOS imagers have a low voltage operation and low power consumption; CMOS imagers are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS imagers allow random access to the image data; and CMOS imagers have lower fabrication costs as compared with the conventional CCDs since standard CMOS processing techniques may be used. Additionally, CMOS imagers exhibit low power consumption because only one row of pixels at a time needs to be active during readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.
In a conventional CMOS pixel, input photons are converted to a corresponding electrical signal by, for example, a pinned photodiode. Readout circuitry couples the converted electrical signal in the form of an output voltage from a row transistor to an output terminal. In applications, a column of CMOS pixels may be coupled to the same output terminal. By selectively applying a row address signal to the gate of a selected row transistor, a selected one of the CMOS pixels may be coupled to the output terminal.
A prior art method for converting an analog signal present on a column output terminal to a digital signal for use by digital imager circuitry using A/D conversion requires two analog-to-digital converters (hereinafter ADC or ADCs) per column to obtain a large dynamic range per column. There is a high and low gain ADC. The high gain ADC is relatively immune to noise but saturates at a relative low input signal level. The second ADC has a low front end gain and provides for a much larger dynamic range of input but has relatively high referred electron noise. The two ADC outputs are spliced to form a single data signal with fewer bits having low noise and large dynamic range.
For example, the high gain ADC provides a saturation level of 1000 e/pixel (i.e., charges per pixel) relative to a pixel full signal of 25,000 e/pixel. The second ADC has low front end gain and provides for an input signal of up to 25,000 e/pixel at saturation but has relatively high noise because of low front end gain. The two spliced ADC output form a single digital signal having noise of about 2 e/pixel (rms) and a full signal of 25,000 e/pixel. When employing this ADC architecture, the pixel itself needs to provide an output signal over this full dynamic range.
For imagers that operate at relatively high data rates, such as one having 5 Megapixels and configured to operate at 100 fps, typically 8 to 16 digital output ports may be required. For the dual ADC per column approach using 11-bit ADCs, about 174 extra bonds pads and package pins are required. This results in higher packaging costs, greater camera complexity and higher on-chip power dissipation. Increased chip power dissipation is undesirable because it may result in a higher dark current, resulting in an imager that has reduced sensitivity or a need for increased cooling.
Accordingly, what would be desirable, but has not yet been provided, is a CMOS imager readout transistor circuit that switches between a low voltage-per-charge (V/e−) ratio and a high voltage-per-charge (V/e−) to enable low noise performance. Also desirable is a CMOS imager having a single ADC per column capable of achieving both low noise and a large full signal (dynamic range).